Wafer test method

专利摘要:
It is an object of the present invention to provide a wafer test method that can reduce package materials and processing time. The present invention is a wafer test method for measuring dielectric film characteristics of a capacitor contacted with a junction region of a wafer, wherein the wafer test applies a predetermined voltage to a wafer on which a capacitor is formed before a package process to apply stress to the dielectric film. Characterized in that.
公开号:KR19980053656A
申请号:KR1019960072784
申请日:1996-12-27
公开日:1998-09-25
发明作者:이대원；정철；황원종
申请人:김영환；현대전자산업 주식회사；
IPC主号:

专利说明:

Wafer Test Method
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer test method, and more particularly, to a wafer test method capable of carrying out a burn-in test before a package process.
In general, wafers fab-out in a package manufacturing process of a semiconductor device are packaged by gathering only the die after the electrical probe test (EDS), and then performing a burn-in test.
Among them, in the conventional DRAM device, in order to measure the dielectric film characteristics of the capacitor, a predetermined stress is applied to the packaged DRAM device to inspect the property.
However, in the electrical probe test described above, when packaged and burn-in after being hardened, a large number of packages fail. For example, if the hard dies are 100pcs after the electrical probe test, these hard dies are packaged and subjected to a burn-in test, of which 5-10pcs fail after burn-in or after bare chip mounting. This causes losses of as much as 5-10%.
That is, although 5-10% of the hard chips do not need to be packaged, there is a problem that unnecessary materials and process costs are invested due to the packaging.
Accordingly, the present invention has been made to solve the above problems, and provides a wafer test method that can measure the dielectric film characteristics of the semiconductor DRAM device prior to the package process, thereby reducing the material and the process cost used during the package process. It aims to do it.
1 is a diagram in which a wafer is placed on a chuck to measure the characteristics of a wafer on which a device is formed, in accordance with the present invention;
2 is a view for explaining a wafer test method according to the present invention.
Explanation of symbols on the main parts of the drawings
1: wafer chuck 2: wafer
3: probe card 4: voltage source
21 junction region 22 gate insulating film
23 gate electrode 24 interlayer insulating film
25: storage node electrode 26: dielectric film
27: plate electrode
In order to achieve the above object of the present invention, the present invention is a wafer test method for measuring the dielectric film characteristics of the capacitor and the contact region of the wafer, the wafer test is a predetermined test on the wafer on which the capacitor is formed before the packaging process The voltage is applied to the dielectric layer, characterized in that the stress is applied.
According to the present invention, by applying a predetermined voltage to the substrate in order to apply a predetermined stress to the insulating film of the thin film before the packaging process, only a high quality die is selected and the packaging process is performed, thereby reducing the cost.
EXAMPLE
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1 is a view in which a wafer is placed on a chuck to measure characteristics of a wafer on which a device is formed, and FIG. 2 is a view for explaining a wafer test method according to the present invention. 2 represents a wafer, 3 represents a probe card, and 4 represents a voltage source.
Referring to FIG. 1, the wafer 1 on which the DRAM element is formed is placed in the wafer chuck 2 to measure the dielectric film characteristics of the capacitor. The metal film, contact or the like of the placed wafer 1 is contacted with the needle of the probe card to measure its characteristics, and the dielectric film of the capacitor is subjected to a predetermined stress, and the breakdown characteristic of the insulating film is measured. .
At this time, in order to apply a predetermined stress to the insulating film, a predetermined positive voltage is applied to the wafer while supplying a positive voltage through the voltage source 4 connected to the wafer chuck 1.
Here, applying a predetermined positive voltage to the wafer is for applying a predetermined stress to the wafer, which will be described in more detail.
Referring to FIG. 2, an N-type junction region 21 is formed on a wafer 2, for example, a P-type silicon wafer by impurity ion implantation, and is formed on the wafer 2 between the junction regions 21. The gate electrode 24 including the gate insulating film 23 is formed. In addition, an interlayer insulating film 24 is formed on the resultant layer, the interlayer insulating film 24 is etched to expose the junction region 21, and then the storage node electrode 25 and the dielectric are brought into contact with the exposed junction region 21. The film 26 and the plate electrode 27 are formed to form a capacitor. At this time, before the voltage is applied, the wafer 2 is in a floating state, and a reverse bias is formed between the junction region and the P-type wafer so that stress is not applied into the dielectric. On the other hand, when a predetermined voltage, preferably 1/2 · Vcc (voltage for driving a DRAM element) voltage is applied by the voltage source connected to the wafer chuck 1, the junction region 21 contacted with the storage node electrode 25. ) And the wafer 2 are forward biased, and stress is applied to the dielectric layer 26 through the storage node electrode 25.
Thus, the insulating film characteristics are measured.
As described in detail above, according to the present invention, by applying a predetermined voltage to the substrate in order to apply a predetermined stress to the insulating film of the thin film before the packaging process, by performing a packaging process by selecting only a good die, The cost is reduced.

权利要求:
Claims (3)
[1" claim-type="Currently amended] A wafer test method for measuring dielectric film characteristics of a capacitor contacted with a junction region of a wafer, wherein the wafer test applies stress to the dielectric film by applying a predetermined voltage to the wafer on which the capacitor is formed before the package process. Wafer test method.
[2" claim-type="Currently amended] The method of claim 1, wherein the voltage applied to the wafer is one half of the voltage for driving a device formed on the wafer.
[3" claim-type="Currently amended] The method of claim 1, wherein the wafer is a P-type silicon wafer.

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同族专利:

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公开号 | 公开日

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1996-12-27|Application filed by 김영환, 현대전자산업 주식회사

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1996-12-27|Priority to KR1019960072784A

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1998-09-25|Publication of KR19980053656A

优先权:

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申请号 | 申请日 | 专利标题

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KR1019960072784A|KR19980053656A|1996-12-27|1996-12-27|Wafer test method|